Moore's Law posits that the number of transistors that can be inexpensively placed on an integrated circuit increases exponentially over time, doubling approximately every two years. Moore's Law was based upon an observation made by Intel co-founder Gordon E. Moore in a 1965 publication. This theory has held true for almost half a century of transistor technology development. State of the art semiconductor designers and manufacturers, however, are encountering more and more obstacles, as the device dimensions get smaller. As designers attempt to insert greater capacity into tiny structures, many issues arise with respect to timing, power, signal integrity, leakage current, thermal gradients and reliability problems (like electromigration).
Designers have attempted to combat the issues resulting from increasing densities by relying upon design-for-manufacturing (DFM) techniques and restricted design rules (RDRs). DFM and RDR techniques can help to obtain adequate yields for some nanometer scale implementations. As the scale of the transistor decreases, however, DFM and RDR techniques become relatively ineffective. More particularly, DRM and RDR techniques are not capable, in smaller nanometer scale logic implementations, of addressing problems relating to electromigration, hot carrier degradation, thin and vulnerable gate oxides, unpredicted process variations, and undetected manufacturing defects.
Conventional development cycles for logic devices, such as next generation processors, typically require multiple iterations of design, layout, fabrication, and post-processing design to achieve an acceptable yield for a given logic device. Typically, the initial fabrication runs for a new logic device design, especially when designing at a smaller geometry, will yield around 5% to 10% of functioning devices. Significant work must then be done to alter the design, layout, and manufacture of the logic device to remove defects from the design and the fabrication process and increase the yield percentage. Often times, the iterative redesign process is lengthy and expensive, sometimes lasting longer and consuming more resources than the initial design cycle. If the yield percentage for a particular new logic device design cannot be improved to approximately 60% to 80% of functioning product, then the design will have to abandoned.
At the current scale of the transistor, it has been possible to rely on iterative post-processing design to improve the yield for logic device fabrication to an acceptable level. Furthermore, as the scale of the transistor decreases, the iterative process of improving yield through redesign and fabrication modifications will no longer be a viable solution. Therefore, the success of nano-scale and smaller logic devices will depend upon their ability to provide some level of defect-tolerance. Conventionally, defect-tolerant logic architectures have been restricted to very high-end implementations. For example, some prior art systems have relied on triple modular redundancy (“TMR”) to provide defect-tolerance. TMR is a defect-tolerant form of N-modular redundancy in which three systems perform a process and the results are processed by a voting system to produce a single output. If any one of the three systems fails, the other two systems can correct and mask the defect. If the voter system fails then the complete system will fail. Therefore, most TMR systems must ensure that the voter system is much more reliable than the other TMR components. While TMR can provide defect-tolerance in some applications, it is a very expensive technology because it requires a 200% or more increase in overhead for a logic device design. Additionally, TMR does not provide a viable means by which to overcome defects during manufacture.
Other prior art systems have proposed the use of a combination of system-level checking, component-level defect diagnosis, and spare-part reconfiguration. In these conventional defect-tolerant systems, the logic device relies upon buffer checker units to detect errors in functional incorrectness and then reconfigures the circuits of the logic device to rely upon spare parts included in the device to replace the function of defective components. These conventional defect-tolerant systems are largely inefficient and ineffective because of the significant amount of overhead required to support the system-level checking functions and the overhead required to include a sufficient set of spare parts for reconfiguration. In many logic device implementations, each circuit is unique; thus, such conventional defect-tolerant systems would need to have a spare part for every part in the device. For the majority of implementations, this level of overhead is simply not feasible.
Therefore, it would be advantageous to provide an apparatus and method for efficiently and effectively providing defect-tolerant logic devices.
Additionally, it would be advantageous to provide an apparatus and method to provide a defect-tolerant logic device with a low overhead.
Additionally, it would be advantageous to provide an improved system and method for correcting a defective transistor.